Design of High-Speed Links: A Look at Modern VLSI Design

Good VLSI system design has always required understanding of both the key system goals and the capabilities of the underlying technology. The need for designers to be able to understand and trade-off issues at different abstraction levels has recently become more important as we have moved from an era where systems were limited by the number of devices that could be fabricated on a die, to current systems which are limited by global constraints like power. Maximum performance now means maximal efficiency, and designers need to trade-off circuit, architecture and system issues to create the most efficient overall design.

This talk demonstrates the kinds of trade-offs needed by looking at the problem of high-speed chip-to-chip communication. Today's high-speed interfaces are limited by the bandwidth of the communication channel, tight power constraints and noise sources that differ from those in standard communication systems. The wire bandwidth limitations make straight circuit solutions inefficient, and the power and area constraints make standard digital communication approaches infeasible. Efficient solutions require bridging the fields of digital communications, optimization, statistical and dynamic system modeling, with system architecture, mixed-signal and digital circuit design, After describing the issues that high-speed I/Os need to overcome, we create a model that correctly represents the statistics of the various noise sources that affect the system's performance. This model estimates the performance limits of the system, and also finds the components which most limit the link performance. This allows us to allocate our limited area and power resources to those issues that are most critical to overall performance.

Using these models we are able to design low-cost equalization techniques for today's baseband links and also predict the necessary link architectures for the future, higher data rates. In addition the link models can now be used in global system optimization to allow the system designer to partition the total energy between chip communication and internal computation, for best overall performance.