13M044VHD - Hardware Verification in Digital Integrated Systems 2

Course specification
Course title		Hardware Verification in Digital Integrated Systems 2
Acronym		13M044VHD
Study programme		Electrical Engineering and Computing
Module		Applied Mathematics, Audio and Video Technologies, Biomedical and Nuclear Engineering, Computer Engineering and Informatics, Electronics and Digital Systems, Energy Efficiency, Information and Communication Technologies, Microwave Engineering, Nanoelectronics and Photonics, Power Systems - Networks and Systems, Power Systems - Renewable Energy Sources, Power Systems - Substations and Power Equipment, Signals and Systems, Software Engineering
Type of study		master academic studies
Lecturer (for classes)		asst. professor PhD Jelena Popović Božović
Lecturer/Associate (for practice)		asst. professor PhD Jelena Popović Božović
Lecturer/Associate (for OTC)		asst. professor PhD Vladimir Petrović asst. professor PhD Jelena Popović Božović
ESPB		6.0	Status	elective
Condition		VLSI Systems Design
The goal		Introduction to advanced procedures for hardware verification in digital integrated systems at core level and system level. Learning advanced methodologies, languages and tools for hardware verification.
The outcome		Students will overcome the procedure of functional verification of hardware modules using advanced verification techniques.
Contents
Contents of lectures		Advanced verification techniques in design of digital integrated systems, goals. Functional and formal verification. Verification languages, System Verilog vs. e, SystemC. Directed verification, constrained random metric driven verification. Register level model in UVM (Universal Verification Methodology). Creating of test plan and Verification Environment. Constrained random tests. Coverage.
Contents of exercises		Design of a verification enviroment for a hardware core using register level model in UVM.
Literature
Andreas Meyer, Principles of Functional Verification, Newnes, 2003. (Original title) Chris Spear, G. Tumbush, SystemVerilog for Verifcation - A Guide to Learning the Testbench Language Features, 2012. (Original title) Universal Verifcation Methodology (UVM) 1.1 User's Guide, Accelera, Maj 2011. (Original title)
Number of hours per week during the semester/trimester/year
Lectures	Exercises	OTC	Study and Research	Other classes
2	1	2
Methods of teaching		Lectures - Power Point presentations. Individual student's work on the projects.
Knowledge score (maximum points 100)
Pre obligations		Points	Final exam	Points
Activites during lectures		0	Test paper	30
Practical lessons		20	Oral examination	0
Projects		50
Colloquia		0
Seminars		0