13E114VLSI - Computer Systems for VLSI

Course specification
Course title Computer Systems for VLSI
Acronym 13E114VLSI
Study programme Electrical Engineering and Computing
Module Computer Engineering and Informatics
Type of study bachelor academic studies
Lecturer (for classes)
Lecturer/Associate (for practice)
Lecturer/Associate (for OTC)
ESPB 6.0 Status elective
Condition None.
The goal Introduce students to hardware description languages (VHDL, Verilog, SystemVerilog, MaxJ). Introduce students to design flow of computer systems for VLSI. Provide students with ability to design, verify and synthesize computer systems. Introduce students to FPGA technology. Introduce students to FPGA based supercomputers for dataflow processing.
The outcome Students will get introduced with constructs of VHDL and Verilog, and generate the ability to use them. Students will get introduced to UVM and basic SystemVerilog constructs. Students will generate the ability to generate configuration and configure FPGA. Students will get the ability for programming FPGA based supercomputers for dataflow processing.
URL to the subject page
Contents of lectures Design flow of computer systems. Basic constructs in VHDL and Verilog for behavioral modeling, dataflow modeling and structural modeling of computer systems. Introduction to UVM, to basic components and their relationships. Basic constructs of SystemVerilog. Model of FPGA based supercomputer for dataflow processing. Introduction to basic constructs of MaxJ language.
Contents of exercises Solving practical problems (VHDL, Verilog, MaxJ). Using the CAD tools. Example design of processor resources and interconnections. Design, simulation, and synthesis of functional processor for FPGA technology.
  1. Milutinovic V., SURVIVING THE DESIGN OF a 200MHz MICROPROCESSOR, IEEE Computer Society Press, USA (best seller);
  2. Mencer O, Dataflow Programming with MaxCompiler, Maxeler Technologies;
  3. Ashenden P., The Designer's Guide to VHDL, 3rd Edition, Morgan Kaufmann;
  4. Coffman K., Real World FPGA Design with VERILOG, Prentice-Hall;
Number of hours per week during the semester/trimester/year
Lectures Exercises OTC Study and Research Other classes
2 2 1
Methods of teaching lectures, exercises, laboratory exercises
Knowledge score (maximum points 100)
Pre obligations Points Final exam Points
Activites during lectures 0 Test paper 50
Practical lessons 20 Oral examination 0
Colloquia 30
Seminars 0