13E044VHD - Hardware Verification in Digital Integrated Systems
Course specification | ||||
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Course title | Hardware Verification in Digital Integrated Systems | |||
Acronym | 13E044VHD | |||
Study programme | Electrical Engineering and Computing | |||
Module | ||||
Type of study | bachelor academic studies | |||
Lecturer (for classes) | ||||
Lecturer/Associate (for practice) | ||||
Lecturer/Associate (for OTC) | ||||
ESPB | 6.0 | Status | elective | |
Condition | Introduction to VLSI Systems Design | |||
The goal | Introduction to hardware verification procedures in digital integrated systems at core level and system level. Introduction to methodologies, languages and tools for hardware verification. Using the Universal Verification Methodology and System Verilog language. | |||
The outcome | Students had the basic knowledge of the functional hardware verification using UVM and System Verilog language. | |||
Contents | ||||
URL to the subject page | http://tnt.etf.bg.ac.rs/~oe4vhd/ | |||
URL to lectures | https://teams.microsoft.com/l/team/19%3ae8JJSncZT6M5_G_V3_m_IfP2vFFdt13Mg--wfqtq63M1%40thread.tacv2/conversations?groupId=273dccd0-759b-4e4c-8ddf-575b0e5b2205&tenantId=1774ef2e-9c62-478a-8d3a-fd2a495547ba | |||
Contents of lectures | Verification of digital integrated systems, goals, types. Functional core-level and system-level verification. High-level Verification Languages, System Verilog, e language, SystemC. Methodologies. UVM, the architecture of the Universal Verification Component. Creating a test plan, designing a verification environment, directly assigning tests and constrained random tests, analyzing coverage. | |||
Contents of exercises | Design of a verification enviroment for a hardware core using UVM and System Verilog. | |||
Literature | ||||
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Number of hours per week during the semester/trimester/year | ||||
Lectures | Exercises | OTC | Study and Research | Other classes |
2 | 1 | 2 | ||
Methods of teaching | Lectures - Power Point presentations. Individual student's work on the projects. | |||
Knowledge score (maximum points 100) | ||||
Pre obligations | Points | Final exam | Points | |
Activites during lectures | 0 | Test paper | 40 | |
Practical lessons | 0 | Oral examination | 0 | |
Projects | 60 | |||
Colloquia | 0 | |||
Seminars | 0 |