13E113AOR1 - Computer Architecture and Organization 1

Course specification
Course title		Computer Architecture and Organization 1
Acronym		13E113AOR1
Study programme		Electrical Engineering and Computing
Module		Computer Engineering and Informatics
Type of study		bachelor academic studies
Lecturer (for classes)		professor PhD Zaharije Radivojević
Lecturer/Associate (for practice)		asst. MA Uroš Radenković, electrical and computer engineer asst. MA Predrag Obradović, electrical and computer engineer
Lecturer/Associate (for OTC)		asst. MA Uroš Radenković, electrical and computer engineer asst. MA Predrag Obradović, electrical and computer engineer
ESPB		6.0	Status	mandatory
Condition		Computer Architecture
The goal		Introduce concepts of hierarchical memory system, RISC architecture and pipeline organization.
The outcome		By the end of this course, students will be able to: understand structure and functioning of a hierarchical memory system; understand RISC architecture and basic concepts of pipeline organization; use literature with the aim to deepen their knowledge in these fields.
Contents
URL to the subject page		https://rti.etf.bg.ac.rs/rti/ri3aor/index.html
URL to lectures		https://teams.microsoft.com/l/team/19%3a1f89b6e69f704f5fa8c3350859595efe%40thread.tacv2/conversations?groupId=4a6dbb52-29d4-46a1-b0b7-5146e71e7efd&tenantId=1774ef2e-9c62-478a-8d3a-fd2a495547ba
Contents of lectures		Virtual memory. Types of virtual memories and translation look-aside buffers. Cache memory. Mapping techniques, replacement algorithms and operating memory updating. Memory. Memory interleaving. Integration of memory and input/output systems. RISC architecture and pipeline organization. Instruction phases and pipeline stages. Hazards. Techniques for avoiding and decreasing negative hazard effects.
Contents of exercises		Virtual memory. Types of virtual memories and translation look-aside buffers. Cache memory. Mapping techniques, replacement algorithms and operating memory updating. Memory. Memory interleaving. Integration of memory and input/output systems. RISC architecture and pipeline organization. Instruction phases and pipeline stages. Hazards. Techniques for avoiding and decreasing negative hazard effects.
Literature
J. Đorđević, Computer Architecture and Organization , http://rti.etf.bg.ac.rs/rti/ri3aor/literatura/predavanja/ J. Đorđević et al., Computer Architecture and Organization , Collection of problems, http://rti.etf.bg.ac.rs/rti/ri3aor/literatura/zbirka/ Hennessy, Patterson, Computer Architecture. A Quantitative Approach (6th Edition), Morgan Kaufmann, 2017. Patterson, Hennessy, Computer Organization and Design: The Hardware-Software Interface (5th Edition), Morgan Kaufmann, 2013. William Stallings - Computer Organization and Architecture Designing for Performance (10th Edition), Pearson, 2015.
Number of hours per week during the semester/trimester/year
Lectures	Exercises	OTC	Study and Research	Other classes
2	2	1
Methods of teaching		Lectures, exercises and laboratory exercises.
Knowledge score (maximum points 100)
Pre obligations		Points	Final exam	Points
Activites during lectures		0	Test paper	30
Practical lessons		20	Oral examination	0
Projects
Colloquia		50
Seminars		0