13D041FSP - Phase Locked Loops

Course specification
Course title Phase Locked Loops
Acronym 13D041FSP
Study programme Electrical Engineering and Computing
Module Electronics
Type of study doctoral studies
Lecturer (for classes)
Lecturer/Associate (for practice)
    Lecturer/Associate (for OTC)
      ESPB 9.0 Status elective
      Condition no
      The goal To qualify students to analyze and design phase locked loops. To qualify students to aplly phase locked loops.
      The outcome Operational knowledge in application and design of phase locked loops in frequency synthesis and synchronization problems.
      Contents of lectures Principles. Classification. Mix-signal PLL. PLL performance in presence of noise, in locked and unlocked state. PLL order. Application of FLL. Frequency synthesis basics. Single-loop and multi loop architectures. High order PLL. Stability, All digital PLL. Architectures. Discretization effects. Frequency domain analysis. Applications. Software PLL.
      Contents of exercises no
      1. Ronald Best, Phase Locked Loops, theory design and applications
      2. Behzad Razavi Phase-Locking in High-Performance Systems: From Devices to Architectures
      3. Dan H. Wolave Phase-Locked Loop Circuit Design
      Number of hours per week during the semester/trimester/year
      Lectures Exercises OTC Study and Research Other classes
      Methods of teaching lectures
      Knowledge score (maximum points 100)
      Pre obligations Points Final exam Points
      Activites during lectures 0 Test paper 0
      Practical lessons 0 Oral examination 30
      Colloquia 0
      Seminars 70