13M114PAR - Computer Architecture And Compiler Parallelism

Course specification
Course title Computer Architecture And Compiler Parallelism
Acronym 13M114PAR
Study programme Electrical Engineering and Computing
Type of study master academic studies
Lecturer (for classes)
Lecturer/Associate (for practice)
Lecturer/Associate (for OTC)
ESPB 6.0 Status elective
Condition Computer architecture and organisation I
The goal Understanding the limits of parallel performance, the parallelism at the instruction level, parallelism of loops, detection and use of parallelism in hardware
The outcome Profound understanding of superscalar and VLIW processors, optimization for parallel execution in modern compilers and models of parallelism
Contents of lectures Parallelism at the instruction level. Data dependencies and data dependency graphs. Trace scheduling. Speculative execution. Parallelism in loops. Loop data dependency graphs. Software pipelining. Vector supercomputers, Very Large Instruction Machines (VLIW) and Superscalar processors. Multicore processors. Hyperthreading.
Contents of exercises Using simulators
  1. Zoran Jovanovic: Instruction level of parallelism, ATC Avangarda, Belgrade 2006
Number of hours per week during the semester/trimester/year
Lectures Exercises OTC Study and Research Other classes
2 2 1
Methods of teaching Classroom courses, education using simulators, clarifying details of parts of the course after students have learnt those parts
Knowledge score (maximum points 100)
Pre obligations Points Final exam Points
Activites during lectures 0 Test paper 0
Practical lessons 0 Oral examination 70
Colloquia 30
Seminars 0