13E044VHD - Hardware Verification in Digital Integrated Systems

Course specification
Course title		Hardware Verification in Digital Integrated Systems
Acronym		13E044VHD
Study programme		Electrical Engineering and Computing
Module		Applied Mathematics, Audio and Video Communications, Biomedical and Environmental Engineering, Computer Engineering and Informatics, Electronics, Electronics and Digital Systems, Energy Efficiency, Microwave Engineering, Nanoelectronics and Photonics, Power Systems - Networks and Systems, Power Systems - Renewable Energy Sources, Power Systems - Substations and Power Equipment, Signals and Systems, Software Engineering, System Engineering and Radio Communications
Type of study		bachelor academic studies,master academic studies
Lecturer (for classes)		asst. professor PhD Jelena Popović Božović
Lecturer/Associate (for practice)		asst. professor PhD Jelena Popović Božović
Lecturer/Associate (for OTC)		asst. professor PhD Vladimir Petrović asst. professor PhD Jelena Popović Božović
ESPB		6.0	Status	elective
Condition		VLSI Systems Design
The goal		Introduction to hardware verification procedures in digital integrated systems at core level and system level. Introduction to methodologies, languages and tools for hardware verification. Using the Universal Verification Methodology and System Verilog language.
The outcome		Students had the basic knowledge of the functional hardware verification using UVM and System Verilog language.
Contents
Contents of lectures		Verification as a procedure in the design of digital integrated systems, goals. Types of functional verification, formal verification. High-level verification languages. Verification methodologies, directed verification, constrained random metric driven verification. UVM, UVC, Verification Environment. Top testbench, test. Creating a test plan, constrained random tests. Coverage.
Contents of exercises		Design of a verification enviroment for a hardware core using UVM and System Verilog.
Literature
Andreas Meyer, Principles of Functional Verification, Newnes, 2003. (Original title) Chris Spear, G. Tumbush, SystemVerilog for Verifcation - A Guide to Learning the Testbench Language Features, 2012. (Original title) Universal Verifcation Methodology (UVM) 1.1 User's Guide, Accelera, Maj 2011. (Original title)
Number of hours per week during the semester/trimester/year
Lectures	Exercises	OTC	Study and Research	Other classes
2	1	2
Methods of teaching		Lectures - Power Point presentations. Individual student's work on the projects.
Knowledge score (maximum points 100)
Pre obligations		Points	Final exam	Points
Activites during lectures		0	Test paper	30
Practical lessons		20	Oral examination	0
Projects		50
Colloquia		0
Seminars		0